MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1193

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
0
ADDRESS OFFSETS
1
0x30XXWC
0x30XXW0
0x30XXW2
0x30XXW4
0x30XXW6
0x30XXW8
0x30XXWA
0x30XXWE
2
0
0
0
3
1
1
1
0
0
= Written By RCPU
= Written By TPU
Channel Function Select xxxx – ID Function Number.
Host Sequence
Host Service Request
Channel Priority
Channel Interrupt Enable 0 – Channel Interrupt Disabled
Channel Interrupt Status 0 – Channel Interrupt Not Asserted
NAME
0
MPC561/MPC563 Reference Manual, Rev. 1.2
1
2
Figure D-25. ID Parameters
TPU3_ID
3
Assigned during microcode assembly.
See
xx – Not Used
00 – No Action
01 – Read TPU ROM version
10 – Not Used
11 – Not Used
00 – Disabled
01 – Low Priority
10 – Medium Priority
11 – High Priority
1 – Channel Interrupt Enabled
1 – Channel Interrupt Asserted
PARAMETER RAM
4
CONTROL BITS
= Written by RCPU and TPU
= Unused Parameters
Table D-1
5
6
OPTIONS
7
BITS
8
9
ROM_REVISION
10 11 12 13 14 15
W = Channel Number
For address offsets: XX=41 for
TPU_A, 45 for TPU_B
YY=40 for TPU_A,
See
44 for TPU_B
Table 19-24
0x30YY1C – 0x30YY1E
0x30YY0C – 0x30YY12
0x30YY18 – 0x30YY1A
0x30YY14 – 0x30YY16
ADDRESSES
0x30YY0A
0x30YY20
TPU3 ROM Functions
Param 0
Param 1
Param 2
Param 3
Param 4
Param 5
Param 6
Param 7
D-41