MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 271

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

6.2.2.2
The SIU interrupt controller contains the following registers: SIPEND, SIPEND2 and SIPEND3 (interrupt
pending registers), SIMASK, SIMASK2 and SIMASK3 (interrupt mask registers), SIEL, SIVEC, SISR2
and SISR3.
The SIPEND and SIMASK registers are used when the interrupt controller is configured for regular,
MPC555/MPC556 compatible, operation. SIPEND2, SIPEND3, SIMASK2, SIMASK3, SISR2 and
SISR3 registers are used only when the interrupt controller is operating in enhanced interrupt mode.
SIPEND, SIPEND2 and SIPEND3 are 32-bit registers. Each bit in the register corresponds to an interrupt
request. The bits associated with internal exceptions indicate, if set, that an interrupt service is requested.
These bits reflect the status of the internal requesting device, and will be cleared when the appropriate
actions are initiated by software in the device itself. Writing to these bits has no effect.
The bits associated with the IRQ pins have a different behavior depending on the sensitivity defined for
them in the SIEL register. When the IRQ is defined as a “level” interrupt the corresponding bit behaves in
a manner similar to the bits associated with internal interrupt sources, (i.e., it reflects the status of the IRQ
pin). This bit can not be changed by software, it will be cleared when the external signal is negated. When
the IRQ is defined as an “edge” interrupt, if the corresponding bit is set, it indicates that a falling edge was
detected on the line. The bit must be reset by software by writing a ‘1’ to it.
The following acronym definitions apply to the various bits implemented in the SIU interrupt controller
registers.
Freescale Semiconductor
30:31
Bits
26
27
28
29
SIU Interrupt Controller Registers
SIZEN
CONT
Name
TRAC
—
—
IMBIRQn
Name
IRQn
IRMn
LVLn
Table 6-14. SIU Interrupt Controller – Bit Acronym Definitions
Control attribute. CONT drives the internal bus control bit attribute as follows:
0 Access to MPC561/MPC563 control register, or control cycle access
1 Access to global address map
Reserved
Trace attribute. TRAC controls the internal bus program trace attribute as follows:
0 Program trace
1 Not program trace
External size enable control bit. SIZEN determines how the internal bus size attribute is driven:
0 Drive size from external bus signals TSIZE[0:1]
1 Drive size from SIZE0, SIZE1 in EMCR
Reserved
Table 6-13. EMCR Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Intermodule Bus Interrupt Level n Request
Interrupt Signal n Request
Interrupt Level n Request
Interrupt Signal n Mask
Description
Description
System Configuration and Protection
6-31