MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 763

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

17.9.3.3
IPM mode is selected by setting MODE[0:3] to 0b0010.
This mode allows the period of an input signal to be determined by capturing two consecutive rising edges
or two consecutive falling edges; successive input captures are done on consecutive edges of the same
polarity. The edge sensitivity is defined by the EDPOL bit in the MDASMSCR register.
This mode also allows the software to determine the logic level on the input signal at any time by reading
the PIN bit in the MDASMSCR register (refer to
polarity is detected, the 16-bit counter bus value is latched into the 16-bit data register A. Data in register
B1 is transferred to data register B2 and the data in register A is transferred to register B1.
On this first capture the FLAG line is not activated, and the value in register B2 is meaningless. On the
second and subsequent captures, the FLAG line is activated when the data in register A is transferred to
register B1.
When the second edge of the same polarity is detected, the counter bus value is latched into data register
A, the data in register B1 is transferred to data register B2, the FLAG line is activated to signify that the
beginning and end points of a complete period have been captured, and finally the data in register A is
transferred to register B1. This sequence of events is repeated for each subsequent capture. Reading data
register B returns the value in register B2.
Freescale Semiconductor
Mode selection; EDPOL = 1 (Channel A capture on falling edge, Channel B capture on rising edge)
B1 is an internal register, not accessible to software
Counter
Register B1
Register B2
Register A
16-bit
Bus
FLAG bit
signal
Input
Input Period Measurement (IPM) Mode
0x0500
0xxxxx
0xxxxx
0xxxxx
Edge Trigger
Figure 17-16. Input Pulse Width Measurement Example
Rising
0x1000
0xxxxx
0x1000
0xxxxx
MPC561/MPC563 Reference Manual, Rev. 1.2
Pulse 1
Edge Trigger
Pulse 1 = Reg A- Reg B
1
Falling
Flag set
0x1100
= 0x0100
0x1100
0x1000
0x1000
2
3
Figure
Edge Trigger
Rising
FLAG reset
by software
17-17). When the first edge having the selected
0x1400
0x1100
0x1400
0x1000
Pulse 2
Edge Trigger
Pulse 2 = Reg A- Reg B
1
Falling
Flag set
Modular Input/Output Subsystem (MIOS14)
0x1525
0x1400
0x1400
= 0x0125
0x1525
FLAG reset
by software
2
3
Edge Trigger
Rising
0x1525
0x16A0
0x1400
0x16A0
17-31