MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 195

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

When an alignment exception is taken, instruction execution resumes at offset 0x00600 from the physical
base address indicated by MSR[IP].
3.15.4.7
A program exception occurs when no higher priority exception exists and one or more of the following
exception conditions, which correspond to bit settings in SRR1, occur during execution of an instruction:
The register settings for program exceptions are shown in
Freescale Semiconductor
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System floating-point enabled exception — A system floating-point enabled exception is
generated when the following condition is met as a result of a move to FPSCR instruction, move
to MSR (mtmsr) instruction, or return from interrupt (rfi) instruction:
(MSR[FE0] | MSR[FE1]) and- FPSCR[FEX] = 1.
Notice that in the RCPU implementation of the PowerPC ISA architecture, a program interrupt is
not generated by a floating-point arithmetic instruction that results in the condition shown above;
a floating-point assist exception is generated instead.
Privileged instruction — A privileged instruction type program exception is generated by any of
the following conditions:
— The execution of a privileged instruction (mfmsr, mtmsr, or rfi) is attempted and the processor
— The execution of mtspr or mfspr where SPR0 = 1 in the instruction encoding (indicating a
— a valid internal-to-the-processor special-purpose register; or
— an external-to-the-processor special-purpose register (either valid or invalid).
Trap — A trap type program exception is generated when any of the conditions specified in a trap
instruction is met.
is operating at the user privilege level (MSR[PR] = 1).
supervisor-access register) and MSR[PR] = 1 (indicating the processor is operating at the user
privilege level), provided the SPR instruction field encoding represents either:
Program Exception (0x0700)
For load or store instructions that use register indirect with index
addressing, the DSISR can be set to the same value that would have resulted
if the corresponding instruction uses register indirect with immediate index
addressing had caused the exception. Similarly, for load or store instructions
that use register indirect with immediate index addressing, DSISR can hold
a value that would have resulted from an instruction that uses register
indirect with index addressing. (If there is no corresponding instruction, no
alternative value can be specified.)
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
Table
3-28.
Central Processing Unit
3-51