MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 283

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

6.2.2.4.6
The real-time clock register is a 32-bit read write register. It contains the current value of the real-time
clock. A write to the RTC resets the seconds timer to zero. This register is locked after reset by default.
Unlocking is accomplished by writing 0x55CC AA33 to its associated key register. See
“Keep-Alive Power Registers Lock
Freescale Semiconductor
PORESET
Reset
Bits
0:7
Field
Addr
10
11
12
13
14
15
8
9
Field
Addr
MSB
0
RTCIRQ
Name
SEC
ALR
ALE
RTF
RTE
Real-Time Clock Register (RTC)
SIE
MSB
4M
—
0
Figure 6-35. Real-Time Clock Status and Control Register (RTCSC)
1
Real-time clock interrupt request. Thee bits determine the interrupt priority level of the RTC.
Refer to
Once per second interrupt. This status bit is set every second. It should be cleared by the
software.
Alarm interrupt. This status bit is set when the value of the RTC equals the value programmed in
the alarm register.
Reserved
Real-time clock source
0 RTC assumes that it is driven by 20 MHz to generate the seconds pulse.
1 RTC assumes that it is driven by 4 MHz
Second interrupt enable. If this bit is set, the RTC generates an interrupt when the SEC bit is set.
Alarm interrupt enable. If this bit is set, the RTC generates an interrupt when the ALR bit is set.
Real-time clock freeze. If this bit is set, the RTC stops while FREEZE is asserted.
Real-time clock enable
0 RTC is disabled
1 RTC is enabled
2
RTCIRQ
Section 6.1.4, “Enhanced Interrupt
3
Figure 6-36. Real-Time Clock Register (RTC)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 6-19. RTCSC Bit Descriptions
4
Mechanism.”
0000_0000_000
5
6
7
Unaffected
0x2F C224
SEC
0x2F C220
RTC
8
Description
ALR
Controller” for interrupt level encoding.
9
—
10
4M
11
U
System Configuration and Protection
SIE
12
ALE
000
13
Section 8.8.3.2,
RTF
14
LSB
31
RTE
LSB
15
U
6-43