MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 847

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

19.4.8
The host service request field selects the type of host service request for the time function selected on a
given channel. The meaning of the host service request bits is determined by time function microcode. See
Appendix D, “TPU3 ROM
Package for more information.
Freescale Semiconductor
SRESET
SRESET
SRESET
SRESET
Field
Addr
Field
Field
Addr
Addr
Field
Addr
CH[15:0]
Name
MSB
MSB
MSB
Host Service Request Registers (HSRRn)
MSB
0
0
0
0
CH 7
CH 15
CH 7
CH 15
1
1
1
1
Encoded host sequence. The host sequence field selects the mode of operation for the time function
selected on a given channel. The meaning of the host sequence bits depends on the time function
specified.
2
2
Figure 19-16. HSRR0 — Host Service Request Register 0
Figure 19-17. HSRR1 — Host Service Request Register 1
2
2
CH 14
CH 6
CH 14
CH 6
Functions,” the TPU Reference Manual and the Freescale TPU Literature
Figure 19-14. HSQR0 — Host Sequence Register 0
Figure 19-15. HSQR1 — Host Sequence Register 1
3
3
3
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 19-13. HSQRn Bit Descriptions
4
4
4
4
CH 13
CH 5
CH 5
CH 13
0x30 401A (TPU_A), 0x30 441A (TPU_B)
0x30 4016 (TPU_A), 0x30 4416 (TPU_B)
0x30 4014 (TPU_A), 0x30 4414 (TPU_B)
0x30 4018 (TPU_A), 0x30 4418 (TPU_B)
5
5
5
5
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
6
6
6
6
CH 12
CH 4
CH 12
CH 4
7
7
7
7
Description
8
8
8
8
CH 11
CH 3
CH 11
CH 3
9
9
9
9
10
10
10
10
CH 10
CH 2
CH 10
CH 2
11
11
11
11
12
12
12
12
CH 1
CH 9
CH 1
CH 9
Time Processor Unit 3
13
13
13
13
14
14
14
14
CH 0
CH 8
CH 0
CH 8
LSB
LSB
LSB
LSB
15
15
15
15
19-17