MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1402

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

BPU 3-4
BQ2 13-19
BR 9-7
Branch
Branch latch control (BLC) 19-12
Branch processing unit 3-4
branch target buffer 4-14
Break frame 15-52
Breakpoint
Breakpoint counter A value and control register 23-45
Breakpoint counter B value and control register 23-46
breakpoints 23-9
BRKNOMSK 23-50
BRx registers 10-32
BTB 4-14
BURST 9-4
burst indicator (BURST), 9-37
burst inhibit (BI), 9-40
burst read cycle (illustration), 9-21
burst transfer, 9-17
burst write cycle (illustration), 9-26
Bus
bus busy (BB), 9-34
bus exception control cycles, 9-45
bus grant (BG), 9-33
bus interface
Index-2
prediction 3-5
processing unit 3-5
trace enable 3-21
asserted flag (BKPT) 19-14
flag (PCBK) 19-14
monitor 6-17
off interrupt
bus control signals, 9-2
bus operation
bus operations, 9-8
bus transfer signals, 9-1
features, 9-1
signal descriptions, 9-3
(BOFFINT) 16-35
address transfer phase related signals, 9-37
arbitration phase, 9-32
basic transfer protocol, 9-8
burst mechanism, 9-18
burst transfer, 9-17
bus exception control cycles, 9-45
single beat transfer
single beat transfer, 9-9
storage reservation, 9-42
termination signals, 9-40
single beat read flow, 9-9
single beat write flow, 9-9
,
3-5
,
,
13-40
9-37
,
14-20
,
14-41
,
9-11
MPC561/MPC563 Reference Manual, Rev. 1.2
Bus interface unit (BIU) 13-2
bus request (BR), 9-33
bus signals (illustration), 9-3
BUSY 16-16
BYP 13-30
Bypass mode 13-35
BYTES field 3-19
C
CA bit 3-19
cache control instructions, 3-43
CALRAM
CAN2.0B
CANCTRL0 16-27
CANCTRL1 16-28
CANCTRL2 16-30
CANICR 16-27
Carry 3-19
CCL 19-13
CCW 13-2
censorship states 21-30
C
CF1 13-21
CF2 13-22
CFSR 19-15
CGBMSK 23-48
CH 19-15
CHAN 13-31
CHANNEL 19-16
Channel
Charge sharing 13-76
F
components 13-51
receive message buffer code 16-5
CLPS 22-8
operation modes 22-4
privileges 22-5
system 16-3
assignments
conditions latch (CCL) 19-13
interrupt
invalid 13-31
number (CHAN) 13-31
orthogonality 19-4
priority registers 19-18
register breakpoint flag (CHBK) 19-14
reserved 13-31
13-75
multiplexed 13-32
nonmultiplexed 13-31
enable
request level (CIRL) 19-15
status (CH) 19-19
/disable field (CH) 19-15
,
,
14-73
,
,
,
19-18
,
14-22
14-23
13-27
13-35
,
,
22-9
14-32
,
,
19-19
,
14-2
,
14-31
22-10
,
,
14-51
14-73
,
14-28
,
14-32
,
14-2
Freescale Semiconductor