MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 969

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Chapter 24
READI Module
The READI module provides real-time development capabilities for RCPU-based MCUs in compliance
with the Nexus IEEE-ISTO 5001-1999. This module provides development support capabilities for MCUs
in single chip mode, without requiring address and data signals for internal visibility. The development
features supported are program trace, data trace, watchpoint trace, ownership trace, run-time access to the
MCU’s internal memory map, and access to RCPU internal registers during halt, via the auxiliary port.
The auxiliary port, along with RCPU development features (such as background debug mode and
watchpoints) supports all software and hardware development in single chip mode. The auxiliary port,
along with (on-chip) calibration RAM, allows calibration variable acquisition and calibration constant
tuning in single chip mode, for automotive powertrain development systems.
24.1
The READI module is compliant with Class 3 of the IEEE-ISTO 5001-1999. The following features are
implemented:
Freescale Semiconductor
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Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow
discontinuities (direct and indirect branches, exceptions etc.), allowing the development tool to
interpolate what transpires between the discontinuities. Thus static code may be traced.
Data trace via data write messaging (DWM) and data read messaging (DRM). This provides the
capability for the development tool to trace reads and/or writes to (selected) internal memory
resources. Data trace also allows for calibration variable acquisition in automotive powertrain
development systems.
— Two data trace windows with programmable address range and access attributes. Data trace
Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership trace by
providing visibility of which process ID or operating system task is activated. An ownership trace
message is transmitted to indicate when a new process/task is activated, allowing development
tools to trace process/task flow.
Features Summary
windowing reduces the requirements on the auxiliary port bandwidth by constraining the
number of trace locations.
In this section the bit numbering in the register definitions of tool mapped
registers follows the Nexus IEEE-ISTO 5001 - 1999 bit numbering
convention of MSB = bit 31 and LSB = bit 0, unlike the MPC500 standard
(MSB = bit 0 and LSB = bit 31). The bit description tables list the bit
numbering and Nexus bit numbering.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
24-1