MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1052

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

READI Module
DSDI message fields of the development port access message are explained in
DSDO message fields of the development port access message are explained in
24-84
.
1
2
Start
Ready
The “Freeze” status is set to (1) when the CPU is in debug mode and to (0) otherwise.
The “Download Procedure in progress” status is asserted (0) when Debug port in the Download procedure and is
negated (1) otherwise.
(0)
(0)
(0)
(0)
1
1
1
1
1
Header
Mode
Header
0
0
1
1
1
0
0
1
1
Status [0:1]
Control
0
1
0
1
1
0
1
0
1
Table 24-34. Development Port Access: DSDO Field
Table 24-33. Development Port Access: DSDI Field
Trap enable
0011111
Bits 0:6
MPC561/MPC563 Reference Manual, Rev. 1.2
Freeze
status
0
Bit 0
1
Instruction / Data (32 Bits)
Procedure
Download
progress
CPU Instruction
Bit 1
in
CPU Data
Data
2
Does not exist
Does not exist
Does not exist
Data
Data
(Depending on Input Mode)
Bits 7:31
Bits 2:31 or 2:6 —
1’s
1’s
1’s
Negate breakpoint requests
Table
Table
Transfer Instruction
Valid Data from CPU
Sequencing Error
CPU Interrupt
Null
Control Register
Transfer data to
Transfer Data
Trap Enable
to the CPU.
Freescale Semiconductor
Function
24-33.
to CPU
to CPU
24-34.
NOP
Function