MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 808

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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Peripheral Pin Multiplexing (PPM) Module
18.2
The PPM occupies 100 bytes of address space, arranged as 50 16-bit entries. All registers must be read or
written through half-word (16-bit) accesses. Reserved register addresses return zeros when read and
cannot be written to.
18-2
Access
— A_T2CLK to B_T2CLK
S/U
S/U
S
S
S
S
S
T
1
2
1
1
1
1
Programming Model
3
3
MPC555
Register Name
TX_CONFIG_1
TX_CONFIG_2
RX_CONFIG_1
RX_CONFIG_2
Parallel TX/RX Protocol
Table 18-1
PPMMCR
RX_DATA
PPMTCR
PPMPCR
Reserved
Reserved
Reserved
Reserved
N=31
Figure 18-1. N-Signal I/O Compared with PPM I/O
0
1
N data signals
shows the memory map for the PPM module.
MPC561/MPC563 Reference Manual, Rev. 1.2
External
Device
Table 18-1. PPM Memory Map
0x30 5C0A
0x30 5C0C
0x30 5C0E
0x30 5C00
0x30 5C02
0x30 5C04
0x30 5C06
0x30 5C08
0x30 5C10
0x30 5C12
0x30 5C14
0x30 5C16
0x30 5C18
Address
Receives data from RX_SHIFTER on SAMP[0:2] update rate
MPC563
MPC561/
PPM TX/RX Protocol
Module Configuration Register
Test Configuration Register
TX Output Configuration
TX Output Configuration
RX Input Configuration
RX Input Configuration
6 signals (maximum 4 data signals)
PPM Control Register
TSYNC
TCLK
TX1
TX0
RX1
RX0
Usage
External
Device
Freescale Semiconductor

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