MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 502

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Legacy Mode Operation
13.5.1
Queue 1 has priority over queue 2 execution. The following cases show the conditions under which queue
1 asserts its priority:
13.5.2
The pause feature can be used to divide queue 1 and/or queue 2 into multiple sub-queues. A sub-queue is
defined by setting the pause bit in the last CCW of the sub-queue.
Figure 13-23
shown with four CCWs in each sub-queue and queue 2 has two CCWs in each sub-queue.
13-38
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When a queue is not active, a trigger event for queue 1 or queue 2 causes the corresponding queue
execution to begin.
When queue 1 is active and a trigger event occurs for queue 2, queue 2 cannot begin execution until
queue 1 reaches completion or the paused state. The status register records the trigger event by
reporting the queue 2 status as trigger pending. Additional trigger events for queue 2, which occur
before execution can begin, are captured as trigger overruns.
When queue 2 is active and a trigger event occurs for queue 1, the current queue 2 conversion is
aborted. The status register reports the queue 2 status as suspended. Any trigger events occurring
for queue 2 while queue 2 is suspended are captured as trigger overruns. Once queue 1 reaches the
completion or the paused state, queue 2 begins executing again. The programming of the RESUME
bit in QACR2 determines which CCW is executed in queue 2. Refer to
Register 2
When simultaneous trigger events occur for queue 1 and queue 2, queue 1 begins execution and
the queue 2 status is changed to trigger pending.
Queue Priority
Paused Sub-Queues
shows the CCW format and an example of using pause to create sub-queues. Queue 1 is
(QACR2)” for more information.
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 13.3.7, “Control
Freescale Semiconductor