MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 423
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
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Manufacturer:
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With dual mapping, aliasing of address spaces may occur. This happens when the region is dual-mapped
into a region which is also mapped into one of the four regions available in the memory controller. If code
or data is written to the dual-mapped region, care must be taken to avoid overwriting this code or data by
normal accesses of the chip-select region.
There is a match if:
Care must also be taken to avoid overwriting “normal” CSx data with dual-mapped code or data.
One way to avoid this situation is by disabling the chip-select region and enabling only the dual-mapped
region (DMBR[DME] = 1, but BRx[V] = 0).
Freescale Semiconductor
•
•
The attributes for the access are taken from one of the base and option registers of the appropriate
chip select
The chip-select region selected is determined by the CS line select bit field
“Dual-Mapping Base Register
where BA represents the bit field in the DMBR register.
bus_address[0:16] == {0000000,ISB[0:2],0,BA[1:6]}
MPC561/MPC563 Reference Manual, Rev. 1.2
(DMBR)”).
Figure 10-19
illustrates the phenomenon.
(Section 10.9.5,
Memory Controller
Eqn. 10-1
Eqn. 10-2
10-25
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