MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 643

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

15.6.4
The QSPI uses a dedicated 160-byte block of static RAM accessible by both the QSPI and the CPU to
perform queued operations. The RAM is divided into three segments: 32 command control bytes, 64
transmit data bytes, and 64 receive data bytes.
Once the CPU has set up a queue of QSPI commands, written the transmit data segment with information
to be sent, and enabled the QSPI, the QSPI operates independently of the CPU. The QSPI executes all of
the commands in its queue, sets a flag indicating completion, and then either interrupts the CPU or waits
for CPU intervention.
QSPI RAM is organized so that one byte of command data, one word of transmit data, and one word of
receive data correspond to each queue entry, 0x0 to 0x2F.
The CPU initiates QSPI operation by setting up a queue of QSPI commands in command RAM, writing
transmit data into transmit RAM, then enabling the QSPI. The QSPI executes the queued commands, sets
a completion flag (SPIF), and then either interrupts the CPU or waits for intervention.
There are four queue pointers. The CPU can access three of them through fields in QSPI registers. The
new queue pointer (NEWQP), contained in SPCR2, points to the first command in the queue. An internal
queue pointer points to the command currently being executed. The completed queue pointer (CPTQP),
contained in SPSR, points to the last command executed. The end queue pointer (ENDQP), contained in
SPCR2, points to the final command in the queue.
The internal pointer is initialized to the same value as NEWQP. During normal operation, the command
pointed to by the internal pointer is executed, the value in the internal pointer is copied into CPTQP, the
internal pointer is incremented, and then the sequence repeats. Execution continues at the internal pointer
address unless the NEWQP value is changed. After each command is executed, ENDQP and CPTQP are
Freescale Semiconductor
1
2
3
4
Master in slave out
Master out slave in
Serial clock
Peripheral chip selects
Peripheral chip select
Slave select
Slave select
All QSPI pins (except SCK) can be used as general-purpose I/O if they are not used by the QSPI while the QSPI is operating.
SCK can only be used for general-purpose I/O if the QSPI is disabled.
An output (PCS0) when the QSPI is in master mode.
An input (SS) when the QSPI is in slave mode.
An input (SS) when the QSPI is in master mode; useful in multimaster systems.
Pin Names
3
4
QSPI Operation
2
Mnemonic
PCS[1:3]
PCS0 /
MISO
MOSI
SCK
MPC561/MPC563 Reference Manual, Rev. 1.2
SS
SS
1
Table 15-20. QSPI Pin Functions
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Serial data input to QSPI
Serial data output from QSPI
Serial data output from QSPI
Serial data input to QSPI
Clock output from QSPI clock
Input to QSPI
Outputs select peripheral(s)
Output selects peripheral(s)
Input selects the QSPI
May cause mode fault
Queued Serial Multi-Channel Module
Function
15-25