MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 253

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

The value of the SIVEC register is supplied internally to the BBC module and can be used as an offset to
the branch table start address for the external interrupt relocation feature. Thus a fast way to a specific
interrupt source routine is provided without software overhead. The BBCMCR (see
Module Configuration Register
Relocation Table Base Address Register
in the BBC. Additionally, the SIPEND2 and SIPEND3 registers contain the information about all the
interrupt requests that are asserted at a given time, so that software can always read them.
Freescale Semiconductor
1
2
3
4
The branch table feature can be used only if the BBCMCR[EIR] is set.
This offset is added to the table base address from the EIBDR register.
This is the value in the 8 most significant bits of the SIVEC register.
This vector is reserved and normally is not generated. It may be generated, if any other interrupt source disappears,
before being acknowleged by the RCPU as a result of any change in the interrupt scheme, module stopping, masking
interrupt sources in a module by application software while interrupts are enabled in the RCPU by setting MSR[EE].
Number
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
When the enhanced interrupt controller is enabled the SIPEND and
SIMASK registers are not used.
Table 6-4. Priority of Interrupt Sources—Enhanced Operation (continued)
Priority Level
Lowest
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(BBCMCR)”) and EIBADR (see
MPC561/MPC563 Reference Manual, Rev. 1.2
(EIBADR)”) registers must be programmed to enable this feature
Interrupt Source
Description
IMB_IRQ 20
IMB_IRQ 21
IMB_IRQ 22
IMB_IRQ 23
IMB_IRQ 24
IMB_IRQ 25
IMB_IRQ 26
IMB_IRQ 27
IMB_IRQ 28
IMB_IRQ 29
IMB_IRQ 30
IMB_IRQ 31
EXT_IRQ6
EXT_IRQ7
Level 6
Level 7
NOTE
Offset in Branch
Table (Hex)
Section 4.6.2.5, “External Interrupt
0x0100
0x0108
0x0110
0x0118
0x0120
0x0128
0x0130
0x0138
0x0140
0x0148
0x0150
0x0158
0x0160
0x0168
0x0170
0x0178
1
,
System Configuration and Protection
2
SIVEC Interrupt Code
Section 4.6.2.1, “BBC
10000000
10000100
10001000
10001100
10010000
10010100
10011000
10011100
10100000
10100100
10101000
10101100
10110000
10110100
10111000
10111100
3
6-13