MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 220

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Burst Buffer Controller 2 Module
U-bus access mode of the RAM is activated by the BBCMCR[DCAE] bit setting (see
“BBC Module Configuration Register
the U-bus and cannot be accessed by the ICDU logic.
In this mode:
4.4.1.1
The DECRAM module does not acknowledge U-bus accesses that violate the configuration defined in the
BBCMCR. This causes the machine check exception for the internal RCPU or an error condition for the
MPC561/MPC563 external master.
4.4.1.2
The bus interface and DECRAM control logic are powered by V
by a separate power pin (IRAMSTBY).
4.5
The burst buffer controller contains a branch target buffer (BTB) to reduce the impact of branches on
processor performance. Following is a summary of the BTB features:
The BTB consists of eight branch target entries (BTE). Refer to
fully associative cache. Each entry contains a tag and several data buffers related to this tag.
4.5.1
When the RCPU generates a change of flow (COF) address for instruction fetch, the BTB control logic
compares it to the tag values currently stored in the tag register file where the following events can happen:
4-14
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The DECRAM supports word, half-word and byte operations.
The DECRAM is emulated to be 32 bits wide. For example: a load access from offset 0 in the
DECRAM will deliver the concatenation of the first word in each of the DECRAM banks when
RAM 1 contains the 16 LSB of the word and RAM 2 contains the 16 MSB.
Load accesses at any width are supplied with 32 bits of valid data.
The DECRAM communicates with the U-bus pipeline but does not support pipelined accesses to
itself. If a store operation is second in the U-bus pipe, the store is carried out immediately and the
U-bus acknowledgment is performed when the previous transaction in the pipe completes.
Burst access is not supported.
Software controlled BTB enable/disable, inhibit, and invalidate
User transparent — no user management required
Branch Target Buffer
BTB Operation
Memory Protection Violations
DECRAM Standby Operation Mode
Instructions running from the DECRAM should not also perform store
operations to the DECRAM.
MPC561/MPC563 Reference Manual, Rev. 1.2
(BBCMCR)”). In this mode the DECRAM can be accessed from
NOTE
DD
Figure
supply. The memory array is supplied
4-5. All entries are managed as a
Freescale Semiconductor
Section 4.6.2.1,