MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1408

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

L
L2U 11-1
L2U module configuration register (L2U_MCR) 11-13
L2U_GRA 11-16
L2U_MCR 11-13
L2U_RAx 11-15
L2U_RBAx 11-14
LBRK 23-43
LBUF 16-29
L-bus support
L-bus to U-bus interface unit 11-1
LCTRL1 23-47
LCTRL2 23-48
LE bit 3-22
Least significant bit (LSB) 13-36
Length of delay after transfer (DTL) 15-19
Link register 3-19
Little endian mode 3-22
LJSRR 13-33
LJURR 13-33
Load/store unit 3-4
Lock
Loop
LOOPQ 15-21
LOOPS 15-47
low power stop 6-23
Low power stop (LPSTOP)
Lowest buffer transmitted first (LBUF) 16-29
Low-power
LR 3-5
LSB 13-36
LSU 3-4
LW0EN 23-49
LW0IA 23-49
LW0IADC 23-49
LW0LA 23-49
LW0LADC 23-49
LW0LD 23-49
LW0LDDC 23-49
LW1EN 23-49
LW1IA 23-49
LW1IADC 23-49
LW1LA 23-50
Index-8
modes of operation 11-3
control register 1 23-47
control register 2 23-48
/release/busy mechanism 16-16
mode
QSM 15-6
stop mode enable (STOP)
(LOOPS) 15-47
TPU 19-11
,
3-19
,
3-6
,
14-38
,
,
14-35
14-35
,
3-6
,
14-38
MPC561/MPC563 Reference Manual, Rev. 1.2
LW1LADC 23-50
LW1LD 23-50
LW1LDDC 23-50
M
M 15-47
MA 13-14
Machine
Machine check
machine check
mapping
Mask
Master
master
MBISM 17-13
MC 24-11
MCE 23-42
MCEE 23-43
MCIE bit 3-47
MCPSM 17-16
MCPSMSCR 17-18
MCPWM D-22
MDASM submodule 17-70
MDASMAR 17-41
MDASMBR 17-42
MDASMSCR 17-44
MDASMSCRD 17-43
ME bit 3-21
memory controller
memory map 1-11
Message
check enable 3-21
state register 3-20
status save/restore register 0 3-23
status save/restore register 1 3-23
enable 3-47
exception
dual 10-26
EEPROM 10-24
examples for normal/extended messages 16-8
registers (RX) 16-7
/slave mode select (MSTR) 15-18
external
registers 10-31
TPU 19-1
buffer
enable 3-47
arbitration phase 9-32
address map 16-24
code for RX/TX buffers 16-5
deactivation 16-14
structure 16-4
,
15-52
,
3-47
,
D-30
Freescale Semiconductor