MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 201

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Execution resumes at offset 0x01000 from the base address indicated by MSR[IP].
3.15.4.14 Implementation-Dependent Instruction Protection Exception (0x1300)
The implementation-specific instruction storage protection error interrupt occurs in the following cases:
The register settings for instruction protection exceptions are shown in
Freescale Semiconductor
1
•
•
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Machine State Register (MSR)
Machine State Register (MSR)
The fetch access violates storage protection and MSR[IR] = 1.
The fetch access is to guarded storage and MSR[IR] = 1.
Register Name
Register Name
Table 3-35. Register Settings following an Instruction Protection Exception
Table 3-34. Register Settings following a Software Emulation Exception
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
DCMPEN
Other
16:31
Other
Bits
Bits
5:15
ME
ME
0:2
LE
LE
All
IP
IP
3
4
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Set to the effective address of the instruction that caused the
exception
Set to 1 if the fetch access was to a guarded storage when
MSR[IR] = 1, otherwise clear to 0
Set to 1 if the storage access is not permitted by the protection
mechanism (IMPU in BBC) and MSR[IR] = 1; otherwise clear
to 0
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[IR]
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
No change
Cleared to 0
Cleared to 0
No change
Cleared to 0
Description
Description
Table
3-35.
Central Processing Unit
3-57