MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 671

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

where SCxBR is in the range {1, 2, 3, ..., 8191}.
The SCI receiver operates asynchronously. An internal clock is necessary to synchronize with an incoming
data stream. The SCI baud rate generator produces a receive time sampling clock with a frequency 16
times that of the SCI baud rate. The SCI determines the position of bit boundaries from transitions within
the received waveform, and adjusts sampling points to the proper positions within the bit period.
Table 15-30
clock speed is 1250 Kbaud.
15.7.7.4
The PT bit in SCCxR1 selects either even (PT = 0) or odd (PT = 1) parity. PT affects received and
transmitted data. The PE bit in SCCxR1 determines whether parity checking is enabled (PE = 1) or
disabled (PE = 0). When PE is set, the MSB of data in a frame (i.e., the bit preceding the stop bit) is used
for the parity function. For transmitted data, a parity bit is generated. For received data, the parity bit is
checked. When parity checking is enabled, the PF bit in the SCI status register (SCxSR) is set if a parity
error is detected.
Enabling parity affects the number of data bits in a frame, which can in turn affect frame size.
shows possible data and parity formats.
Freescale Semiconductor
shows possible baud rates for a 40-MHz IMB3 clock. The maximum baud rate with this IMB3
Parity Checking
1,250,000.00
Baud Rate
1
57,600.00
38,400.00
32,768.00
28,800.00
19,200.00
14,400.00
Nominal
9,600.00
4,800.00
2,400.00
1,200.00
These rates are based on a 40-MHz IMB3 clock.
600.00
300.00
Table 15-31. Effect of Parity Checking on Data Size
M
0
0
Table 15-30. Examples of SCIx Baud Rates
MPC561/MPC563 Reference Manual, Rev. 1.2
SCxBR
1,250,000.00
Baud Rate
56,818.18
37,878.79
32,894.74
29,069.77
19,230.77
14,367.81
9,615.38
4,807.69
2,399.23
1,199.62
Actual
600.09
299.98
=
------------------------------------------------------------------------
32xSCI Baud Rate Desired
PE
0
1
f SYS
8 data bits
7 data bits, 1 parity bit
Percent
Error
-1.36
-1.36
-0.22
-0.03
-0.03
-0.01
0.00
0.39
0.94
0.16
0.16
0.16
0.02
Result
1
Value of
SCxBR
1042
2083
4167
130
260
521
22
33
38
43
65
87
Queued Serial Multi-Channel Module
1
Table 15-31
15-53