MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 629

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

The port QS data register (PORTQS) latches I/O data. PORTQS writes drive pins defined as outputs.
PORTQS reads return data present on the pins. To avoid driving undefined data, write the first data to
PORTQS before configuring DDRQS.
15.5.1
PORTQS determines the actual input or output value of a QSMCM port pin if the pin is defined as
general-purpose input or output. All QSMCM pins can be used as general-purpose input and/or output.
When the SCIx transmitter is disabled, TXDx is a discrete output; when the SCIx receiver is disabled,
RXDx is a discrete input. Writes to this register affect the pins defined as outputs; reads of this register
return the actual value of the pins.
Freescale Semiconductor
Port QS Data Register (PORTQS)
1
QSMCM Pin
The PORTQS register can be written either as a half-word (16-bit) or as 2
individual bytes (8-bit). This allows the SCI GPIO pin data to written
separately than the QSPI GPIO pin values. This allows either the SCI pins
or the QSPI pins to be used independently as GPIO.
PCS0/SS
SCK/QGPIO6 is a digital I/O pin unless the SPI is enabled (SPE set in SPCR1), in which case
it becomes the QSPI serial clock SCK.
PCS[1:3]
MISO
MOSI
SCK
1
Table 15-8. Effect of DDRQS on QSPI Pin Function
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
MPC561/MPC563 Reference Manual, Rev. 1.2
DDRQS Bit
DDQS[4:6]
DDQS0
DDQS1
DDQS2
DDQS3
NOTE
Bit State
—
—
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Serial data output from QSPI
Serial data output from QSPI
Assertion causes mode fault
Disables chip-select output
Disables slave select input
Serial data input to QSPI
Serial data input to QSPI
Clock output from QSPI
QSPI slave select input
Disables data output
Disables data output
Clock input to QSPI
Disables data input
Disables data input
Chip-select output
Chip-select output
Pin Function
Inactive
Inactive
Queued Serial Multi-Channel Module
15-11