MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 902

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

CALRAM Operation
22.4.5
Stop Operation
The low power stop mode for this module is entered by setting the disable bit (DIS) in the CRAMMCR
register. Reads from and writes to the array during this mode will generate an error.
When the disable bit (DIS) is cleared, the module returns to normal function.
22.4.6
Overlay Mode Operation
For a microcontroller used as a controller for an engine (or other electromechanical device), various
parameters stored in the Flash memory may need to be changed in order to properly tune (calibrate) the
engine. Because Flash memory may not be readily programmed during normal operation of an embedded
controller, portions of the CALRAM array can be overlayed onto the U-bus Flash memory. By allowing
the CALRAM module to overlay portions of Flash memory, parameters normally stored in the Flash may
be tweaked and changed with a development tool both during normal operation and prior to programming
a final, more precise version of the Flash memory.
The overlay is for read-only data and does not affect instruction fetches from the Flash. The data for any
L-bus address which falls in the overlay region of the U-bus Flash will be driven by the CALRAM on the
L-bus. The CALRAM also indicates to the L2U to block the data from the Flash to be driven onto the
L-bus. As far as the RCPU core is concerned, the timing of data coming from the CALRAM appears to be
the same as that from the Flash.
22.4.6.1
Overlay Mode Configuration
Each CALRAM module contains eight overlay regions, each of which is 512 bytes long as shown in
Figure
22-4. All overlay regions of a module are contiguous and each starts at the least significant address
of the region and can increment all the way up to 512 bytes as shown in
Figure
22-5. As described in
section
Section 22.5.2, “CALRAM Region Base Address Registers
(CRAM_RBAx)”, CRAM_RBAx
registers allow the programming of the base addresses RBA[11:29] of the U-bus Flash regions and the
RGN_SIZE[0:4] to be overlaid. Note that each region can also be individually disabled by writing 0000 to
RGN_SIZE[0:3]. If the programmed base address is not naturally aligned with respect to the RGN_SIZE
field, the least significant bits of the base address fields can be considered 0’s in order to make the starting
address naturally aligned. In an RBA register, RGN_SIZE[0:3] ={0101} select the size to be 128 bytes,
and even if CRAM_RBAx [25:29] are not all 0’s, they will be considered as 0’s so that the address
becomes 128-byte naturally aligned.
MPC561/MPC563 Reference Manual, Rev. 1.2
22-6
Freescale Semiconductor