MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 333

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
Bits
10
3
4
5
6
7
8
9
PRQEN
DCSLR
MFPDL
STBUC
RTDIV
CQDS
Name
LPML
TBS
Disable clock switching at loss of lock during reset. When DCSLR is clear and limp mode
is enabled, the chip will switch automatically to the backup clock if the PLL losses lock
during HRESET. When DCSLR is asserted, a PLL loss-of-lock event does not cause clock
switching. If HRESET is asserted and DCSLR is set, the chip will not negate HRESET until
the PLL acquires lock.
0 Enable clock switching if the PLL loses lock during reset
1 Disable clock switching if the PLL loses lock during reset
MF and pre-divider lock. Setting this control bit disables writes to the MF and DIVF bits.
This helps prevent runaway software from changing the VCO frequency and causing the
SPLL to lose lock. In addition, to protect against hardware interference, a hardware reset
will be asserted if these fields are changed while LPML is asserted. This bit is writable once
after power-on reset.
0 MF and DIVF fields are writable
1 MF and DIVF fields are locked
LPM lock. Setting this control bit disables writes to the LPM and CSRC control bits. In
addition, for added protection, a hardware reset is asserted if any mode is entered other
than normal-high mode. This protects against runaway software causing the MCU to enter
low-power modes. (The MSR[POW] bit provides additional protection). LPML is writable
once after power-on reset.)
0 LPM and CSRC bits are writable
1 LPM and CSRC bits are locked and hard reset will occur if the MCU is not in normal-high
Time base source.
0 Source is OSCCLK divided by either 4 or 16
1 Source is system clock divided by 16
RTC (and PIT) clock divider. At power-on reset this bit is cleared if MODCK[1:3] are all low;
otherwise the bit is set.
0 RTC and PIT clock divided by 4
1 RTC and PIT clock divided by 256
Switch to backup clock control. When software sets this bit, the system clock is switched
to the on-chip backup clock ring oscillator, and the chip undergoes a hard reset. The
STBUC bit is ignored if LME is cleared.
0 Do not switch to the backup clock ring oscillator
1 Switch to backup clock ring oscillator
Clock quarter drive strength — The COM and CQDS bits control the output buffer strength
of the CLKOUT, see
Power management request enable
0 Remains in the lower frequency (defined by DFNL) even if the power management bit in
1 Switches to high frequency (defined by DFNH) when the power management bit in the
mode
the MSR is reset (normal operational mode) or if there is a pending interrupt from the
interrupt controller
MSR is reset (normal operational mode) or there is a pending interrupt from the interrupt
controller
Table 8-9. SCCR Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
8-10.
Description
Clocks and Power Control
8-31