MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 506

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Legacy Mode Operation
13.5.4.3
When the application software wants to execute a single pass through a sequence of conversions defined
by a queue, a single-scan queue operating mode is selected. By programming the MQ field in QACR1 or
QACR2, the following modes can be selected:
In all single-scan queue operating modes, the software must also enable the queue to begin execution by
writing the single-scan enable bit to a one in the queue’s control register. The single-scan enable bits, SSE1
and SSE2, are provided for queue 1 and queue 2 respectively.
Until the single-scan enable bit is set, any trigger events for that queue are ignored. The single-scan enable
bit may be set to a one during the write cycle, which selects the single-scan queue operating mode. The
single-scan enable bit is set through software, but will always read as a zero. Once set, writing the
single-scan enable bit to zero has no effect. Only the QADC64E can clear the single-scan enable bit. The
completion flag, completion interrupt, or queue status are used to determine when the queue has
completed.
After the single-scan enable bit is set, a trigger event causes the QADC64E to begin execution with the
first CCW in the queue. The single-scan enable bit remains set until the queue is completed. After the
queue reaches completion, the QADC64E resets the single-scan enable bit to zero. If the single-scan
enable bit is written to a one or a zero by the software before the queue scan is complete, the queue is not
affected. However, if the software changes the queue operating mode, the new queue operating mode and
the value of the single-scan enable bit are recognized immediately. The conversion in progress is aborted
and the new queue operating mode takes effect.
In the software-initiated single-scan mode, the writing of a one to the single-scan enable bit causes the
QADC64E to internally generate a trigger event and the queue execution begins immediately. In the other
single-scan queue operating modes, once the single-scan enable bit is written, the selected trigger event
must occur before the queue can start. The single-scan enable bit allows the entire queue to be scanned
once. A trigger overrun is captured if a trigger event occurs during queue execution in an edge-sensitive
external trigger mode or a periodic/interval timer mode.
In the periodic/interval timer single-scan mode, the next expiration of the timer is the trigger event for the
queue. After the queue execution is complete, the queue status is shown as idle. The software can restart
the queue by setting the single-scan enable bit to a one. Queue execution begins with the first CCW in the
queue.
13.5.4.3.1
Software can initiate the execution of a scan sequence for queue 1 or 2 by selecting the software initiated
single-scan mode, and writing the single-scan enable bit in QACR1 or QACR2. A trigger event is
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Software initiated single-scan mode
External trigger single-scan mode
External gated single-scan mode
Periodic/Interval timer single-scan mode
Single-Scan Modes
Queue 2 cannot be programmed for external gated single-scan mode.
Software Initiated Single-Scan Mode
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
Freescale Semiconductor