MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 133

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
MODCK[2:3]
SGPIOC5
Signal List
IRQ[6:7]
SGPIOC4
MODCK1
PULL_SEL
TSIZ[0:1]
RD/WR
BURST
IRQ5
TS
BDIP
IRQ4 /
AT2 /
7,12
10
7
10
7
7
/
11
7
7
3
1
/
11
/
Voltage
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
5 V
5 V
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
Controlled
Slew Rate
Option?
Yes
MPC561/MPC563 Reference Manual, Rev. 1.2
No
No
No
No
No
No
No
No
No
No
No
No
No
50 ; 50
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
Drive
Load
(pF)
NA
NA
NA
NA
NA
NA
2
5
PD until reset
negates
PD until reset
negates
PD until PRDS
is set
PU2.6 until reset
negates
PU2.6 until
PRDS is set
PU2.6V until
reset negates
PU2.6 until
SPRDS is set
PU2.6 until reset
negates
PU5, external
pull device
required
PD when driver
not enabled or
until SPRDS is
set
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 when
driver not
enabled or until
SPRDS is set
Reset State
6, 8
6, 8
Hysteresi
Enabled?
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
s
IRQ4
MODCK1 until reset negates,
then IRQ5
MODCK[2:3] until reset
negates, then IRQ[6:7]
PULL_SEL
TSIZ[0:1]
RD/WR
BURST
BDIP
TS
Function After HRESET,
PORESET/TRST
Signal Descriptions
2-35