MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 975
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
Instruction Taken
Instruction Retire
ICTRL
Ownership Trace
Message (OTM)
Public Messages
RCPU
READI
READI signals
RPM
run-time
Sequential Instruction
Snooping
Standard
Superfield
Show Cycle
Transfer Code (TCODE) Message header that identifies the number and/or size of packets to be transferred, and how
TCK / DSCK / MCKI
TDI / DSDI / MDI0
TDO / DSDO / MDO0
Upload
VSYNC
VF
VFLS
Term
An instruction is taken after it has been issued and recognized by the appropriate execution
unit. All resources to perform the instruction are ready, and the processor begins to execute it.
Completion of the instruction issue, execution and writeback stages. An instruction is ready
to be retired if it completes without generating an exception and all instructions ahead of it in
history buffer have completed without generating an exception.
Instruction bus support control register (Refer to
Visibility of process/function that is currently executing.
Messages on the auxiliary signals for accomplishing common visibility and controllability
requirements e.g. DRM and DWM.
Processor that implements the PowerPC-based architecture used in the Freescale MPC500
family of microcontrollers.
Real time Embedded Applications Development Interface.
Refers to IEEE-ISTO 5001 auxiliary port.
Reduced Port Mode. This is the reduced port mode for READI.
RCPU is executing program code in normal mode
Any instruction other than a flow-control instruction or isync.
Monitoring addresses driven by a bus master to detect the need for coherency actions.
The phrase “according to the standard” implies according the IEEE-ISTO 5001 - 1999.
One or more message “fields” delimited by MSEO/MSEI assertion/negation.
The information transmitted between “start-message” and “end-packet” states.
An internal access (e.g., to an internal memory) reflected on the external bus using a
special cycle (marked with a dedicated transfer code). For an internal memory “hit,” an
address-only bus cycle is generated; for an internal memory “miss,” a complete bus cycle is
generated.
to interpret each of the packets.
Multiplexed signal: JTAG Clock or Development Port Clock. MCKI is a READI signal on the
MPC561/MPC563
Multiplexed signal: JTAG Data In or Development Port Serial Data In. MDI0 is a READI signal
on the MPC561/MPC563.
Multiplexed signal: JTAG Data Out or Development Port Serial Data Out. MDO0 is a READI
signal on the MPC561/MPC563
Device sends information to the tool.
Internal RCPU signal
Internal RCPU signal which indicates instruction queue status.
Internal RCPU signal which indicates history buffer flush status.
Table 24-3. Terms and Definitions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Table
23.6.11)
READI Module
24-7
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