MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 384

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

External Bus Interface
In this case, the bus interface block implements a reservation flag for the local bus master. The reservation
flag is set by the bus interface when a load with reservation is issued by the local bus master and the
reservation address is located on the remote bus. The flag is reset (negated) when an alternative master on
the remote bus accesses the same location in a write cycle. If the MPC561/MPC563 begins a memory cycle
to the previously reserved address (located in the remote bus) as a result of an stwcx instruction, the
following two cases can occur:
9-44
•
•
If the reservation flag is set, the buses interface acknowledges the cycle in a normal way
If the reservation flag is reset, the bus interface should assert the KR. However, the bus interface
should not perform the remote bus write-access or abort it if the remote bus supports aborted
cycles. In this case the failure of the stwcx instruction is reported to the RCPU.
MPC500 Device
External Bus
Interface
Figure 9-31. Reservation on Multi-level Bus Hierarchy
MPC561/MPC563 Reference Manual, Rev. 1.2
AT[0:3], RSV, R/W, TS
KR
External Bus (Local Bus)
Q
Remote Bus
R
S
A Master in the Remote Bus Write
to the Reserved Location
ADDR[0:29]
Local Master Accesses with
lwarx
to Remove Bus Address
Freescale Semiconductor
Interface
Bus