MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 375

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

9.5.7.4
The MPC561/MPC563 can be configured at system reset to use the internal bus arbiter. In this case, the
MPC561/MPC563 will be parked on the bus. The parking feature allows the MPC561/MPC563 to skip the
bus request phase, and if BB is negated, assert BB and initiate the transaction without waiting for BG from
the arbiter.
The priority of the external device relative to the internal MPC561/MPC563 bus masters is programmed
in the SIU module configuration register. If the external device requests the bus and the MPC561/MPC563
does not require it, or if the external device has higher priority than the current internal bus master, the
MPC561/MPC563 grants the bus to the external device.
Table 9-4
Freescale Semiconductor
CLKOUT
BR0
BG0
BR1
BG1
BB
and Attributes
TS
TA
ADDR[8:31]
describes the priority mechanism used by the internal arbiter.
Internal Bus Arbiter
Figure 9-26. Bus Arbitration Timing Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
“Turns On” and
Drives Signals
Master 0
(Three-state Controls)
and “Turns Off”
Negates BB
Master 0
“Turns On” and
Drives Signals
Master 1
External Bus Interface
9-35