MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 844

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Time Processor Unit 3
19.4.4
19-14
SRESET
SRESET
13:15
Bits
0:7
10
11
12
8
9
Field
Addr
Field
Addr
TPU3 Interrupt Configuration Register (TICR)
MSB
MSB
0
Name
PCBK
CHBK
SRBK
BKPT
TPUF
0
—
—
1
1
Reserved
Breakpoint asserted flag. If an internal breakpoint caused the TPU3 to enter the halted state, the
TPU3 asserts the BKPT signal on the IMB and sets the BKPT flag. BKPT remains set until the
TPU3 recognizes a breakpoint acknowledge cycle, or until the IMB FREEZE signal is asserted.
Microprogram Counter (µPC) breakpoint flag. PCBK is asserted if a breakpoint occurs because
of a µPC register match with the µPC breakpoint register. PCBK is negated when the BKPT flag
is cleared.
Channel register breakpoint flag. CHBK is asserted if a breakpoint occurs because of a CHAN
register match with the CHAN register breakpoint register. CHBK is negated when the BKPT flag
is cleared.
Service request breakpoint flag. SRBK is asserted if a breakpoint occurs because of any of the
service request latches being asserted along with their corresponding enable flag in the
development support control register. SRBK is negated when the BKPT flag is cleared.
TPU3 FREEZE flag. TPUF is set whenever the TPU3 is in a halted state as a result of FREEZE
being asserted. This flag is automatically negated when the TPU3 exits the halted state because
of FREEZE being negated.
Reserved
Figure 19-7. DSSR — Development Support Status Register
Figure 19-8. TICR — TPU3 Interrupt Configuration Register
2
—
2
3
3
—
MPC561/MPC563 Reference Manual, Rev. 1.2
4
Table 19-9. DSSR Bit Descriptions
4
0x30 4006 (TPU_A), 0x30 4406 (TPU_B)
0x30 4008 (TPU_A), 0x30 4408 (TPU_B)
5
5
6
CIRL
0000_0000_0000_0000
0000_0000_0000_0000
6
7
7
BKPT PCBK CHBK SRBK TPUF
8
Description
8
ILBS
9
9
10
10
11
11
12
12
Freescale Semiconductor
—
13
13
—
14
14
LSB
LSB
15
15