MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 776

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Modular Input/Output Subsystem (MIOS14)
17-44
SRESET
Bits
0
1
2
3
4
5
Field PIN WOR FREN
Addr
FORCA
EDPOL
MSB
Name
FREN
WOR
—
0
PIN
—
0x30 605E, 0x30 6066, 0x30 606E, 0x30 6076, 0x30 607E, 0x30 60DE, 0x30 60E6, 0x30 60EE,
1
Pin Input Status — The pin input status bit reflects the status of the corresponding bit.
Wired-OR bit — In the DIS, IPWM, IPM and IC modes, the WOR bit is not used; reading this bit
returns the value that was previously written.
In the OCB, OCAB and OPWM modes, the WOR bit selects whether the output buffer is
configured for open-drain or totem pole operation. When open-drain mode is selected, the
EDPOL bit is not used; writing to EDPOL will have no effect on the output voltage.
1 Output buffer is open-drain.
0 Output buffer is totem pole.
The WOR bit is cleared by reset.
Freeze enable bit — This active high read/write control bit enables the MDASM to recognize the
MIOB freeze signal.
1 = The MDASM is frozen if the MIOB freeze line is active.
0 = The MDASM is not frozen even if the MIOB freeze line is active.
The FREN is cleared by reset.
Reserved
Polarity bit — In the DIS mode, this bit is not used; reading it returns the last value written.
In the IPWM mode, this bit is used to select the capture edge sensitivity of channels A and B.
1 Channel A captures on a falling edge. Channel B captures on a rising edge.
0 Channel A captures on a rising edge. Channel B captures on a falling edge.
In the IPM and IC modes, the EDPOL bit is used to select the input capture edge sensitivity of
channel A.
1 Channel A captures on a falling edge.
0 Channel A captures on a rising edge.
In the OCB, OCAB and OPWM modes, the EDPOL bit is used to select the voltage level on the
output signal. If open-drain mode is selected via the WOR bit, the EDPOL bit is disabled and
writing to it will have no effect on the output voltage.
1 The complement of the output flip-flop logic level appears on the output signal: a match on
0 The output flip-flop logic level appears on the output signal: a match on channel A sets the
The EDPOL bit is cleared by reset.
Force A bit — In the OCB, OCAB and OPWM modes, the FORCA bit allows the software to force
the output flip-flop to behave as if a successful comparison had occurred on channel A (except
that the FLAG line is not activated). Writing a one to FORCA sets the output flip-flop; writing a
zero to it has no effect.
In the DIS, IPWM, IPM and IC modes, the FORCA bit is not used and writing to it has no effect.
FORCA is cleared by reset and is always read as zero.
Writing a one to both FORCA and FORCB simultaneously resets the output flip-flop.
Figure 17-24. MDASM Status/Control Register (MDASMSCR)
channel A resets the output signal; a match on channel B sets the output signal.
output signal, a match on channel B resets the output signal.
2
—
Table 17-21. MDASMSCR Bit Descriptions
3
MPC561/MPC563 Reference Manual, Rev. 1.2
EDPOL FORCA FORCB
4
5
0x30 60F6, 0x30 60FE
000_0000_0000_0000
6
Description
7
—
8
9
BSL
10
—
11
Freescale Semiconductor
12
13
MODE
14
LSB
15