MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1403
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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CHBK 19-14
CHBMSK 23-48
check stop state 23-26
checkstop 7-3
Checkstop enable 3-47
chip-select
CHSTP bit 23-42
CHSTPE 23-43
CHSTPE bit 3-47
CIE1 13-16
CIE2 13-18
CIER 19-15
CIRL 19-15
CISR 19-8
class, instruction, 3-40
CLKOUT 8-13
CLKOUT to TA, BI assertion (when driven by the Memory
CLKOUT, 9-8
CLKS 19-12
Clock
clocks
CLPS 22-9
CLPS bit 22-8
CMPA–CMPD 23-41
CMPE–CMPF 23-46
CMPG–CMPH 23-47
CNRX/TX pins 16-2
CNTC 23-45
CNTV 23-45
Code
code decompression
Coherency 13-45
coherency 19-4
COLIR 8-36
COMM D-17
Command
Command word pointer (CWP) 13-24
Comparator 13-37
Freescale Semiconductor
global 10-27
block diagram 13-48
frequency 13-48
generation 13-47
phase (CPHA) 15-18
polarity (CPOL) 15-18
requirements 13-52
general system 8-10
message buffer field 16-4
features A-1
modes of A-14
data coherency during reset 7-4
RAM 15-23
Controller) F-21
,
,
,
19-19
,
14-17
14-19
19-19
,
22-9
,
13-52
,
,
14-38
,
14-48
,
22-10
,
F-22
14-51
,
14-49
,
14-46
,
G-21
,
14-51
,
13-27
MPC561/MPC563 Reference Manual, Rev. 1.2
,
14-25
,
14-28
Comparator A–D value registers 23-41
Comparator E–F value registers 23-46
Comparator G–H value registers 23-47
Compare instructions 3-17
Compare size 23-48
Compare type 23-47
Completed queue pointer (CPTQP) 15-22
compressed address generation
compression
compression, code
compression, environment
Condition register 3-16
configuration
configuration word
CONT 15-24
contention, 9-37
Continue (CONT) 15-24
Continuous transfer mode 15-16
Control registers
controlling termination of a bus cycle for a bus error, 9-45
Conversion
conversion queue operation 14-29
Count register 3-19
COUNTA 23-45
COUNTB 23-46
CPHA 15-18
CPOL 15-18
CPR 19-18
CPTQP 15-22
CPU
CR 3-5
direct branches A-4
exceptions A-6
indirect branches A-6
READI A-16
algorithm A-2
features of A-1
implementation of A-11
initialization of A-13
soft reset 7-13
hard reset (RCW) 7-11
0 (QACR0) 13-7
1 (QACR1) 13-7
2 (QACR2) 13-7
QADC64E control register 1 (QACR1) 13-15
QADC64E control register 2 (QACR2) 13-17
command word table (CCW) 13-2
cycle times 13-35
stages 13-29
wait states 13-52
and compare instructions 3-17
14-28
,
3-16
,
,
,
,
14-38
15-35
,
3-19
15-35
,
15-25
14-30
,
23-51
,
,
,
,
,
9-5
,
14-7
14-7
14-7
14-51
,
14-36
23-51
,
3-17
,
A-17
,
13-27
,
13-37
,
,
14-16
14-18
,
Index-3
14-2
,
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