MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 429

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

10.9
The registers in
10.9.1
Freescale Semiconductor
1. In the case of an external master that accesses an internal MPC561/MPC563 module (in slave or
2. If the memory controller serves an external master, then it can support accesses to 32-bit port
3. When the SETA bit in the base register is set, then the timing programming for the various strobes
4. When configuring a chip select for a memory region with the intent to access that region
peripheral mode), if that slave device address also matches one of the memory controller’s regions,
the memory controller will not issue any CS for this access, nor will it terminate the cycle. Thus,
this practice should be avoided. Be aware also that any internal slave access prevents memory
controller operation.
devices only. This is because the MPC561/MPC563 external bus interface cannot initiate extra
cycles to complete an access to a smaller port-size device as it does not own the external bus.
(CS, OE and WE/BE) may become meaningless.
immediately after configuration, then an ISYNC instruction should be executed in order to ensure
that the configuration takes effect before any accesses are initiated.
Programming Model
General Memory Controller Programming Notes
Table 10-6
0x2F C148 — 0x2F C174
0x2F C120 — 0x13F
0x2F C10C
0x2F C11C
0x2F C100
0x2F C104
0x2F C108
0x2F C110
0x2F C114
0x2F C118
0x2F C140
0x2F C144
0x2F C178
Address
are used to control the memory controller.
Table 10-6. Memory Controller Address Map
MPC561/MPC563 Reference Manual, Rev. 1.2
Dual-Mapping Option Register (DMOR)
Dual-Mapping Base Register (DMBR)
Memory Status Register (MSTAT)
Option Register Bank 0 (OR0)
Option Register Bank 1 (OR1)
Option Register Bank 2 (OR2)
Option Register Bank 3 (OR3)
Base Register Bank 0 (BR0)
Base Register Bank 1 (BR1)
Base Register Bank 2 (BR2)
Base Register Bank 3 (BR3)
Reserved
Reserved
Register
Memory Controller
10-31