MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 14

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

11.1
11.2
11.3
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.5
11.5.1
11.5.2
11.5.3
11.6
11.6.1
11.6.2
11.6.3
11.7
11.7.1
11.7.2
11.7.3
11.7.4
11.7.5
11.7.6
11.8
11.8.1
11.8.2
11.8.3
11.8.4
11.8.5
11.8.6
12.1
12.2
12.3
12.4
Freescale Semiconductor
Paragraph
Number
General Features ........................................................................................................... 11-1
Data Memory Protection Unit Features ........................................................................ 11-1
L2U Block Diagram ...................................................................................................... 11-2
Modes Of Operation ..................................................................................................... 11-3
Data Memory Protection ............................................................................................... 11-4
Reservation Support ...................................................................................................... 11-7
L-Bus Show Cycle Support .......................................................................................... 11-9
L2U Programming Model ........................................................................................... 11-12
Features ......................................................................................................................... 12-1
UIMB Block Diagram .................................................................................................. 12-2
Clock Module ............................................................................................................... 12-2
Interrupt Operation ....................................................................................................... 12-3
Normal Mode ............................................................................................................ 11-3
Reset Operation ......................................................................................................... 11-4
Peripheral Mode ........................................................................................................ 11-4
Factory Test Mode .................................................................................................... 11-4
Functional Description .............................................................................................. 11-5
Associated Registers ................................................................................................. 11-6
L-Bus Memory Access Violations ............................................................................ 11-7
Reservation Protocol ................................................................................................. 11-8
L2U Reservation Support ......................................................................................... 11-8
Reserved Location (Bus) and Possible Actions ........................................................ 11-9
Programming Show Cycles .................................................................................... 11-10
Performance Impact ................................................................................................ 11-10
Show Cycle Protocol .............................................................................................. 11-10
L-Bus Write Show Cycle Flow ............................................................................... 11-10
L-Bus Read Show Cycle Flow ................................................................................ 11-11
Show Cycle Support Guidelines ............................................................................. 11-11
U-Bus Access .......................................................................................................... 11-13
Transaction Size ...................................................................................................... 11-13
L2U Module Configuration Register (L2U_MCR) ................................................ 11-13
Region Base Address Registers (L2U_RBAx) ....................................................... 11-14
Region Attribute Registers (L2U_RAx) ................................................................. 11-15
Global Region Attribute Register (L2U_GRA) ...................................................... 11-16
U-Bus to IMB3 Bus Interface (UIMB)
L-Bus to U-Bus Interface (L2U)
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
Chapter 11
Chapter 12
Title
Number
Page
xiv