MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 411

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Note: In this and subsequent timing diagrams in this section, the data bus refers to a read cycle. In a write cycle, the data
10.3.2
Figure 10-9
device. In this case CSx is connected directly to the chip enable (CE) of the memory device and the R/W
line is connected to the R/W in the peripheral device. The CSx line is the strobe output for the memory
access.
Freescale Semiconductor
immediately follows TS.
Peripheral Devices Interface Example
illustrates the basic connection between the MPC561/MPC563 and an external peripheral
Figure 10-8. Memory Devices Interface Basic Timing (ACS = 00, TRLX = 0)
Address
WE/BE
Clock
Data
OE
CS
TS
TA
MPC5xx
Address
RD/WR
Figure 10-9. Peripheral Devices Interface
MPC561/MPC563 Reference Manual, Rev. 1.2
Data
CSx
RD/WR
Address
CE
Data
Peripheral
CSNT = 1, ACS = 00
Memory Controller
10-13