MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 476

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Legacy Mode Operation
The supervisor-only data space segment contains the QADC64E global registers, which include the
QADCMCR, the QADCTEST, and the QADCINT. The supervisor/unrestricted space designation for the
CCW table, the result word table, and the remaining QADC64E registers is programmable.
13.3.2
QADCINT specifies the priority level of QADC64E interrupt requests. The interrupt level for queue 1 and
queue 2 may be different. The interrupt register is read/write accessible in supervisor data space only. The
implemented interrupt register fields can be read and written, reserved bits read zero and writes have no
effect. They are typically written once when the software initializes the QADC64E, and not changed
afterwards.
The QADC64E conditionally generates interrupts to the bus master via the IMB3 IRQ signals. When the
QADC64E sets a status bit assigned to generate an interrupt, the QADC64E drives the IRQ bus. The value
driven onto IRQ[7:0] represents the interrupt level assigned to the interrupt source. Under the control of
ILBS, each interrupt request level is driven during the time multiplexed bus during one of four different
time slots, with eight levels communicated per time slot. No hardware priority is assigned to interrupts.
Furthermore, if more than one source on a module requests an interrupt at the same level, the system
software must assign a priority to each source requesting at that level.
levels on IRQ with ILBS. Refer to
information.
13-12
SRESET
Bit(s)
10:15
0:4
5:9
Field
Addr
QADC64E Interrupt Register (QADCINT)
MSB
0
Name
IRL1
IRL2
—
1
Queue 1 Interrupt Request Level. The IRL1 field establishes the queue 1 interrupt request level.
The 00000 state provides a level 0 interrupt, while 11111 provides a level 31 interrupt. All
interrupts are presented on the IMB3. Interrupt level priority software determines which level has
the highest priority request.
Queue 2 Interrupt Request Level. The IRL2 field establishes the queue 2 interrupt request level.
The 00000 state provides a level 0 interrupt, while 11111 provides a level 31 interrupt. All
interrupts are presented on the IMB3. Interrupt level priority software determines which level has
the highest priority request.
Reserved.
IRL1
2
Figure 13-5. QADC Interrupt Register (QADCINT)
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 13-7. QADCINT Bit Descriptions
Chapter 12, “U-Bus to IMB3 Bus Interface
0x30 4804 (QADCINT_A); 0x30 4C04 (QADCINT_B)
4
5
0000_0000_0000_0000
6
IRL2
7
Description
8
9
Figure 13-6
10
11
(UIMB),” for more
displays the interrupt
12
Freescale Semiconductor
—
13
14
LSB
15