MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 403

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

10.2.3
The WP bit in each base register can restrict write access to its range of addresses. Any attempt to write
this area results in the associated WPER bit being set in the MSTAT.
If an attempt to access an external device results in a write-protect violation, the memory controller
considers the access to be no match. No chip-select line is asserted externally, and the memory controller
does not terminate the cycle. The external bus interface generates a normal cycle on the external bus. Since
the memory controller does not acknowledge the cycle internally, the cycle may be terminated by external
logic asserting TA or by the on-chip bus monitor asserting TEA.
10.2.4
The base address is written to the BRx. The address mask bits for the address are written to the OR. The
address type access value, if desired, is written to the AT bits in the BRx. The ATM bits in the ORx can be
used to mask this value. If address type checking is not desired, program the ATM bits to zero.
Each time an external bus cycle access is requested, the address and address type are compared with each
one of the banks. If a match is found, the attributes defined for this bank in its BRx and ORx are used to
control the memory access. If a match is found in more than one bank, the lowest bank matched handles
the memory access (e.g., bank zero is selected over bank one).
10.2.5
The memory controller supports burst accesses of external burstable memory. To enable bursts, clear the
burst inhibit (BI) bit in the appropriate base register. Burst support is for read only.
Bursts can be four or eight beats depending on the value of the BURST_EN bit in the SIUMCR register
and the BL bit in the BRx register. That is, the memory controller executes up to eight one-word accesses,
but when a modulo eight limit is reached, the burst is terminated (even if fewer than eight words have been
accessed).
When the SIU initiates a burst access, if no match is found in any of the memory controller’s regions then
a burst access is initiated to the external bus. The termination of each beat for this access is externally
controlled.
To support different types of memory devices, the memory controller supports two types of timing for the
BDIP signal: normal and late.
If the memory controller is used to support an external master accessing an external device with bursts, the
BDIP input signal is used to indicate to the memory controller when the burst is terminated.
Freescale Semiconductor
Write-Protect Configuration
Address and Address Space Checking
Burst Support
When an external master accesses a slave on the bus, the internal AT[0:2]
lines reaching the memory controller are forced to 100.
The BDIP signal itself is controlled by the external bus interface logic. Refer
to
Figure 9-13
and
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 9-14
in
NOTE
NOTE
Chapter 9, “External Bus
Interface."
Memory Controller
10-5