MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 713

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

16.5.3
Auto power save mode enables normal operation with optimized power savings. Once the auto power save
(APS) bit in CANMCR is set, the TouCAN looks for a set of conditions in which there is no need for the
clocks to be running. If these conditions are met, the TouCAN stops its clocks, thus saving power. The
following conditions activate auto power save mode:
Freescale Semiconductor
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When the self wake mechanism is activated, the TouCAN tries to receive the frame that woke it
up. (It assumes that the dominant bit detected is a start-of-frame bit.) It will not arbitrate for the
CAN bus at this time.
If the STOP bit is set while the TouCAN is in the bus off state, then the TouCAN enters low-power
stop mode and stops counting recessive bit times. The count continues when STOP is cleared.
To place the TouCAN in low-power stop mode with the self wake mechanism engaged, write to
CANMCR with both STOP and SELFWAKE set, and then wait for the TouCAN to set the
STOPACK bit.
To take the TouCAN out of low-power stop mode when the self wake mechanism is enabled, write
to CANMCR with both STOP and SELFWAKE clear, and then wait for the TouCAN to clear the
STOPACK bit.
The SELFWAKE bit should not be set after the TouCAN has already entered low-power stop
mode.
If both STOP and SELFWAKE are set and a recessive to dominant edge immediately occurs on the
CAN bus, the TouCAN may never set the STOPACK bit, and the STOP bit will be cleared.
To prevent old frames from being sent when the TouCAN awakes from low-power stop mode via
the self wake mechanism, disable all transmit sources, including transmit buffers configured for
remote request responses, before placing the TouCAN in low-power stop mode.
If the TouCAN is in debug mode when the STOP bit is set, the TouCAN assumes that debug mode
should be exited. As a result, it tries to synchronize with the CAN bus, and only then does it await
the conditions required for entry into low-power stop mode.
Unlike other modules, the TouCAN does not come out of reset in low-power stop mode. The basic
TouCAN initialization procedure should be executed before placing the module in low-power stop
mode. (Refer to
If the TouCAN is in low-power stop mode with the self wake mechanism engaged and is operating
with a single system clock per time quantum, there can be extreme cases in which the TouCAN
would wake-up on a recessive to dominant edge which may not conform to the CAN protocol.
TouCAN synchronization is shifted one time quantum from the wake-up event. This shift lasts until
the next recessive-to-dominant edge, which resynchronizes the TouCAN to be in conformance
with the CAN protocol. The same holds true when the TouCAN is in auto power save mode and
awakens on a recessive to dominant edge.
No Rx/Tx frame in progress
No transfer of Rx/Tx frames to and from a serial message buffer, and no Tx frame awaiting
transmission in any message buffer
No CPU access to the TouCAN module
Auto Power Save Mode
Section 16.4.2, “TouCAN
MPC561/MPC563 Reference Manual, Rev. 1.2
Initialization.”)
CAN 2.0B Controller Module
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