MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 972

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

READI Module
24.2.2
Security is provided via the UC3F censorship mechanism. If a UC3F array is in censored mode, reads or
writes to the UC3F will not be allowed (RCPU will not be able to fetch instructions from the UC3F) once
any of the following cases are detected:
24.2.3
Normal operation of the READI module allows for developement support features to be available. These
features include control of the device, access to registers, and the ability to perform data or instruction
trace.
24.2.4
If EVTI is negated at negation of RSTI, the READI module will be disabled. No trace output will be
provided, and output auxiliary port will be three-stated. Any message sent by the tool is ignored.
24.3
With 32-deep message queues, throughput numbers were calculated for the following benchmark codes
[assuming full port mode]:
For reduced port mode, the data trace feature should not be used, or used sparingly, so as not to cause queue
overruns.
24.4
The READI module implements messaging via the auxiliary port according to the IEEE-ISTO 5001 -
1999. Messaging will be implemented via transfer codes (TCODEs) on the auxiliary port. The TCODE
number for the message identifies the transfer format (the number and/or size of packets to be transferred)
and the purpose of each packet.
Public messages outlined in
24-4
•
•
•
•
•
Program trace and/or data trace are enabled
Read/write access is attempted (can be to any address location)
RCPU development access is enabled.
For an example benchmark which had 10.9% direct branches, 2.5% indirect branches, 10.4% data
writes, and 19.3% data reads, approximately 20% of total data trace accesses will be traced.
For another example benchmark which had 9.8% direct branches, 2.8% indirect branches, 6.6%
data writes, and 18.3% data reads, approximately 27% of total data trace accesses will be traced.
Parametrics
Messages
Security
Normal
Disabled
The queue is only 16 messages deep on revisions prior to Rev. D of the
MPC561 and is 16 deep in Rev. B and earlier versions of the MPC563.
Table 24-1
MPC561/MPC563 Reference Manual, Rev. 1.2
are supported by READI.
NOTE
Freescale Semiconductor