MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 553

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

The bus master indicates the supervisor and user space access with the function code bits (FC[2:0]) on the
IMB3. For privilege violations, refer to
of a bus error cycle termination.
The supervisor-only data space segment contains the QADC64E global registers, which include the
QADCMCR, QADCINT and QADCTEST. The supervisor/unrestricted space designation for the CCW
table, the result word table and the remaining QADC64E registers is programmable.
14.3.2
QADCINT specifies the priority level of QADC64E interrupt requests. The interrupt level for queue 1 and
queue 2 may be different. The interrupt register is read/write accessible in supervisor data space only. The
implemented interrupt register fields can be read and written, reserved bits read zero and writes have no
effect. They are typically written once when the software initializes the QADC64E, and not changed
afterwards.
Freescale Semiconductor
•
•
attempts to write unimplemented data space, the QADC64E causes a bus error condition and no
data is written.
Attempts to read assignable data space in the unrestricted access mode when the space is
programmed as supervisor space causes the bus master to assert a bus error condition and no data
is returned.
Attempts to write assignable data space in the unrestricted access mode when the space is
programmed as supervisor space causes the bus master to assert a bus error condition and the
register is not written.
QADC64E Interrupt Register
1
2
3
4 Access to QADCTEST register will act as a reserved/unimplemented register unless in factory
Mode
S/U = Supervisor/Unrestricted
QADC64E bus error = Caused by QADC64E
Master bus error = Caused by bus master
test mode
S/U
U
U
S
S
1
SUPV Bit
0
1
0
1
Table 14-6. QADC64E Bus Error Response
MPC561/MPC563 Reference Manual, Rev. 1.2
QADC64E bus error
Supervisor-Only
Master bus error
Valid access
Valid access
Register
Chapter 9, “External Bus
3
2
Unrestricted Register
Master bus error
Valid access
Valid access
Valid access
Supervisor/
Interface” to determine the consequence
4
3
QADC64E bus error
QADC64E bus error
QADC64E bus error
Master bus error
QADC64E Enhanced Mode Operation
Unimplemented
Reserved/
Register
3
2
2
2
14-11