MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 939

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Entering debug mode is also possible immediately out of reset, thus allowing the debugging of even a
ROM-less system. Using this feature is possible by special programming of the development port during
reset. If the DSCK pin continues to be asserted following SRESET negation (after enabling debug mode)
the processor will take a breakpoint exception and go directly to debug mode instead of fetching the reset
vector. To avoid entering debug mode following reset, the DSCK pin must be negated no later than seven
clock cycles after SRESET negates. In this case, the processor will jump to the reset vector and begin
normal execution. When entering debug mode immediately after reset, bit 31 (development port interrupt)
of the exception cause register (ECR) is set.
When debug mode is disabled all events result in regular interrupt handling.
The internal freeze signal is asserted whenever an enabled event occurs, regardless if debug mode is
enabled or disabled. The internal freeze signal is connected to all relevant internal modules. These modules
can be programmed to stop all operations in response to the assertion of the freeze signal. Refer to
Section 23.5.1, “Freeze
The freeze indication is negated when exiting debug mode. Refer to
Mode.”
The following list contains the events that can cause the CPU to enter debug mode. Each event results in
debug mode entry if debug mode is enabled and the corresponding enable bit is set. The reset values of the
enable bits allow, in most cases, the use of the debug mode features without the need to program the debug
enable register (DER). For more information refer to
(DPDR).”
Freescale Semiconductor
SRESET
DSCK asserts high while SRESET is asserted to enable debug mode operation.
•
•
•
•
CLK
OUT
DSCK
DSCK asserts high following SRESET negation to enable debug mode immediately.
NMI exception as a result of the assertion of the IRQ0_B pin. For more information refer to
Section 3.15.4.1, “System Reset Exception and NMI
Check stop. Refer to
Machine check exception
Implementation specific instruction protection error
Indication.”
0
Section 23.3.1.3, “Check Stop State and Debug
Figure 23-8. Debug Mode Reset Configuration
1
MPC561/MPC563 Reference Manual, Rev. 1.2
2
3
4
5
8
Section 23.6.13, “Development Port Data Register
9
10 11 12
(0x0100).”
Section 23.3.1.6, “Exiting Debug
13 14
Mode,” for more information.
15 16
17
Development Support
23-25