MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 161

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Instructions are provided to test individual CR bits.
3.7.4.1
In most integer instructions, when the CR is set to reflect the result of the operation (that is, when Rc = 1),
and for addic., andi., and andis., the first three bits of CR0 are set by an algebraic comparison of the result
to zero; the fourth bit of CR0 is copied from XER[SO]. For integer instructions, CR0[0:3] are set to reflect
the result as a signed quantity. The EQ bit reflects the result as an unsigned quantity or bit string.
The CR0 bits are interpreted as shown in
into the destination register) is undefined, the value placed in the first three bits of CR0 is undefined.
3.7.4.2
In all floating-point instructions when the CR is set to reflect the result of the operation (that is, when Rc
= 1), the CR1 field (bits 4 to 7 of the CR) is copied from FPSCR[0:3] to indicate the floating-point
exception status. For more information about the FPSCR, see
Control Register
3.7.4.3
When a specified CR field is set by a compare instruction, the bits of the specified field are interpreted as
shown in
instructions.
Freescale Semiconductor
•
CR1 Bit
CR0 Bit
A specified CR field can be the explicit result of an integer compare instruction.
0
1
2
3
0
1
2
3
Table
Floating-point exception (FX). This is a copy of the final state of FPSCR[FX] at the completion of the
instruction.
Floating-point enabled exception (FEX).This is a copy of the final state of FPSCR[FEX] at the completion of
the instruction.
Floating-point invalid exception (VX).This is a copy of the final state of FPSCR[VX] at the completion of the
instruction.
Floating-point overflow exception (OX).This is a copy of the final state of FPSCR[OX] at the completion of
the instruction.
Condition Register CR0 Field Definition
Negative (LT). This bit is set when the result is negative.
Positive (GT). This bit is set when the result is positive (and not zero).
Zero (EQ). This bit is set when the result is zero.
Summary overflow (SO). This is a copy of the final state of XER[SO] at the completion of the instruction.
Condition Register CR1 Field Definition
Condition Register CRn Field — Compare Instruction
3-9. A condition register field can also be accessed by the mfcr, mcrf, and mtcrf
(FPSCR).” The bit settings for the CR1 field are shown in
Table 3-7. Bit Settings for CR0 Field of CR
Table 3-8. Bit Settings for CR1 Field of CR
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
3-7. If any portion of the result (the 32-bit value placed
Description
Description
Section 3.7.3, “Floating-Point Status and
Table
3-8.
Central Processing Unit
3-17