MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 151

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Adherence to the PowerPC ISA architecture can be measured in terms of which of the levels are
implemented.
3.6
The PowerPC ISA architecture defines register-to-register operations for most computational instructions.
Source operands for these instructions are accessed from the registers or are embedded in the instruction
opcode. The three-register instruction format allows specification of a target register distinct from the two
source operands. Load and store instructions transfer data between memory and on-chip registers.
PowerPC ISA-compliant processors have two levels of privilege: supervisor mode (typically used by the
operating environment) and user mode (used by the application software). The programming model
incorporates 32 GPRs, special-purpose registers (SPRs), and several miscellaneous registers.
Supervisor-level access is provided through the processor’s exception mechanism. That is, when an
exception is taken (whether automatically, because of an error or problem that needs to be serviced, or
deliberately, as in the case of a trap instruction), the processor begins operating in supervisor mode. The
access level is indicated by the privilege-level (PR) bit in the machine state register (MSR).
Figure 3-3
of the PowerPC ISA architecture. Note that registers such as the general-purpose registers (GPRs) are
accessed through operands that are part of the instructions. Registers can be accessed explicitly through
specific instructions such as move to special-purpose register (mtspr) or move from special-purpose
register (mftspr), or implicitly as part of an instruction’s execution. Some registers are accessed both
explicitly and implicitly.
Freescale Semiconductor
•
Operating environment architecture (OEA) — defines the memory-management model,
supervisor-level registers, synchronization requirements, and the exception model.
Implementations that conform to the OEA also adhere to the UISA and the VEA.
RCPU Programming Model
illustrates the user-level and supervisor-level RCPU programming models and the three levels
MPC561/MPC563 Reference Manual, Rev. 1.2
Central Processing Unit
3-7