MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 148

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Central Processing Unit
3.4
The PowerPC ISA architecture provides independent floating-point, integer, load/store, and branch
processing execution units, making it possible to implement advanced features such as look-ahead
operations. For example, since branch instructions do not depend on GPRs, branches can often be resolved
early, eliminating stalls caused by taken branches.
Table 3-1
3-4
Branch processing unit (BPU)
Independent Execution Units
Load/store unit (LSU)
summarizes the RCPU execution units.
Unit
Instruction Address Generator
CC unit
Execution Units and Registers Files
MPC561/MPC563 Reference Manual, Rev. 1.2
Includes the implementation of all branch instructions.
Includes implementation of all load and store instructions, whether defined as
part of the integer processor or the floating-point processor.
Table 3-1. RCPU Execution Units
Figure 3-2. Sequencer Data Path
Instruction Memory System
Evaluation
Condition
Branch
Description
Instruction Buffer
Instruction
Pre-fetch
Queue
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Freescale Semiconductor
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