MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 335

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

8.11.2
The PLL, low-power, and reset-control register (PLPRCR) is a 32-bit register powered by the keep-alive
power supply.
Freescale Semiconductor
25:27
29:31
Bits
24
28
PLL, Low-Power, and Reset-Control Register (PLPRCR)
COM[0:1]
DFNL[0:2]
Name
DFNH
00
01
01
10
11
—
—
Reserved
Division factor low frequency. The user can load these bits with the desired divide value
and the CSRC bit to change the frequency. Changing the value of these bits does not result
in a loss of lock condition. These bits are cleared by power-on or hard reset. Refer to
Section 8.5.1, “General System
000 Divide by 2
001 Divide by 4
010 Divide by 8
011 Divide by 16
100 Divide by 32
101 Divide by 64
110 Reserved
111 Divide by 256
Reserved
Division factor high frequency. These bits determine the general system clock frequency
during normal mode. Changing the value of these bits does not result in a loss of lock
condition. These bits are cleared by power-on or hard reset. The user can load these bits
at any time to change the general system clock rate. Note that the GCLKs generated by
this division factor are not 50% duty cycle (i.e. CLKOUT).
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Reserved
Table 8-10. COM and CQDS Bits Functionality
Table 8-9. SCCR Bit Descriptions (continued)
CQDS
MPC561/MPC563 Reference Manual, Rev. 1.2
x
0
1
x
x
Clock Output Enabled Full-Strength Output Buffer, Bus pins full
drive
Clock Output Enabled Half-Strength Output Buffer, Bus pins
reduced drive
Clock Output Enabled Quarter-Strength Output Buffer, Bus pins
reduced drive
Clock Output Disabled, Bus pins full drive
Clock Output Disabled, Bus pins reduced drive
Clocks” and
Description
Figure 8-5
Function
for details on using these bits.
Clocks and Power Control
8-33