MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 207

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Chapter 4
Burst Buffer Controller 2 Module
The burst buffer controller module (BBC) consists of four main functional parts: the bus interface unit
(BIU), the instruction memory protection unit (IMPU), branch target buffer (BTB) and the instruction code
decompressor unit (ICDU). See
Figure
4-1. Information about decompression features of the BBC is found
in
Appendix A, “MPC562/MPC564 Compression
Features.”
The BBC master BIU interfaces between the RCPU instruction port and the internal U-bus and can support
burstable and non-burstable U-bus accesses.
The IMPU allows the instruction memory to be divided into four regions with different protection
attributes. The IMPU compares the attributes of the RCPU memory access request with the attributes of
the appropriate region. If the access is allowed, the proper signals are sent to the BIU. If access to the
memory region is disallowed because the region is protected, an interrupt is sent to the RCPU and the
master BIU cancels U-bus access.
The IMPU is able to relocate the RCPU exception vectors. The IMPU always maps the exception vectors
into the internal memory space of the MPC561/MPC563. This feature is important for a
multi-MPC561/MPC563 system, where, although the internal memories of some controllers are not
shifted to the lower 4 Mbytes, they can still have their own internal exception vector tables with the same
exception addresses issued by their RCPU cores.
The IMPU also supports an MPC561/MPC563-enhanced interrupt controller by extending an exception
vector’s relocation mechanism to translate the RCPU external interrupt exception vector separately and
splitting it into 48 different vectors, corresponding to the code generated by the interrupt controller. See
also
Section 6.1.4.4, “Enhanced Interrupt Controller
Operation.”
The branch target buffer (BTB) improves the performance of the MPC561/MPC563 by holding and
supplying previously accessed or decompressed instructions to the RCPU core. The BTB can be enabled
in either decompression on or off mode.
The ICDU provides decompressed instructions to RCPU in the decompression ON mode and contains a 2
Kbyte RAM (DECRAM) to hold decompression vocabularies. The DECRAM can serve as a general
purpose RAM memory on the U-bus if code compression is not used.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-1