MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 587

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

determine the last valid conversion in the queue. Software must set the single-scan enable bit again and
should clear the PF1 bit before another scan of queue 1 is initiated during the next open gate. The start of
queue 1 is always the first CCW in the CCW table.
Since the condition of the gate is only sampled after each conversion during queue execution, closing the
gate for a period less than a conversion time interval does not guarantee the closure will be captured.
14.4.4.3.4
Both queues can use the periodic/interval timer in a single-scan queue operating mode. The timer interval
can range from 128- to 128-Kbyte QCLK cycles in binary multiples. When the periodic/ interval timer
single-scan mode is selected and the software sets the single-scan enable bit in QACR1 or QACR2 , the
timer begins counting. When the time interval elapses, an internal trigger event is created to start the queue
and the QADC64E begins execution with the first CCW.
The QADC64E automatically performs the conversions in the queue until a pause or an end-of-queue
condition is encountered. When a pause occurs, queue execution stops until the timer interval elapses
again, and then queue execution continues. When the queue execution reaches an end-of-queue situation,
the single-scan enable bit is cleared. Software may set the single-scan enable bit again, allowing another
scan of the queue to be initiated by the periodic/interval timer.
The periodic/interval timer generates a trigger event whenever the time interval elapses. The trigger event
may cause the queue execution to continue following a pause, or may be considered a trigger overrun.
Once the queue execution is completed, the single-scan enable bit must be set again to enable the timer to
count again.
Normally only one queue will be enabled for periodic/interval timer single-scan mode and the timer will
reset at the end-of-queue. However, if both queues are enabled for either single-scan or continuous
periodic/interval timer mode, the end-of-queue condition will not reset the timer while the other queue is
active. In this case, the timer will reset when both queues have reached end-of-queue. See
“Periodic/Interval
The periodic/interval timer single-scan mode can be used in applications which need coherent results, for
example:
14.4.4.4
When the application software wants to execute multiple passes through a sequence of conversions defined
by a queue, a continuous-scan queue operating mode is selected. By programming the MQ1 field in
QACR1 or the MQ2 field in QACR2, the following software initiated modes can be selected:
Freescale Semiconductor
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When it is necessary that all samples are guaranteed to be taken during the same scan of the analog
signals
When the interrupt rate in the periodic/interval timer continuous-scan mode would be too high
In sensitive battery applications, where the single-scan mode uses less power than the software
initiated continuous-scan mode
Software initiated continuous-scan mode
External trigger continuous-scan mode
Continuous-Scan Modes
Periodic/Interval Timer Single-Scan Mode
Timer,” for a definition of periodic/interval timer reset conditions.
MPC561/MPC563 Reference Manual, Rev. 1.2
QADC64E Enhanced Mode Operation
Section 14.4.6,
14-45