MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 601

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Situations S10 and S11
detected for queue 2 while the queue is suspended, the trigger overrun error bit is set, the same as if queue
2 were being executed when a new trigger event occurs. Trigger overrun on queue 2 thus permits the
software to know that queue 1 is taking up so much QADC64E time that queue 2 trigger events are being
lost.
Freescale Semiconductor
Q1
Q2
QS
Q1
Q2
QS
0000
0000
IDLE
IDLE
Q2:
Q2:
IDLE
IDLE
T2
T2
C1
ACTIVE
C1
C1
ACTIVE
(Figure 14-34
0010
0010
C2
C2
Q1:
Q1:
T1
T1
SUSPEND
SUSPEND
ACTIVE
TOR2
C1
ACTIVE
C1
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 14-34. CCW Priority Situation 10
ACTIVE
T2
Figure 14-33. CCW Priority Situation 9
1010
1010
C2
C2
and
PF1
PF1
ACT
0110
Figure
ACTIVE
C2
C1
0110
PF2
PAUSE
0101
C2
PAUSE
PAUSE
14-35) show that when an additional trigger event is
PF2
T2
PAUSE
0101
C3
ACTIVE
0110
T2
ACT
0110
C4
C3
T1
T1
SUSPEND
SUSPEND
TOR2
ACTIVE
C3
ACTIVE
C3
ACTIVE
T2
1010
1010
C4
C4
CF1
CF1
ACT
0010
C3
C4
ACTIVE
0010
QADC64E Enhanced Mode Operation
CF2
C4
CF2
RESUME=1
IDLE
IDLE
RESUME=0
IDLE
0000
IDLE
0000
QADC S10
QADC S9
14-59