MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 241

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Chapter 6
System Configuration and Protection
The MPC561/MPC563 incorporateDMAes many system functions that normally must be provided in
external circuits. In addition, it is designed to provide maximum system safeguards against hardware and
software faults. The system configuration and protection sub-module provides the following features:
Freescale Semiconductor
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System Configuration
configuration of the system according to the particular requirements. The functions include control
of show cycle operation, pin multiplexing, and internal memory map location. System
configuration also includes a register containing part and mask number constants to identify the
part in software.
External Master Modes Support
modes are special modes of operation that allow an alternate master on the external bus to access
the internal modules for debugging and backup purposes.
General-Purpose I/O
for general-purpose I/O. The SGPIO pins are multiplexed with the address and data pins.
Enhanced Interrupt Controller
controller receives interrupt requests from a number of internal and external sources and directs
them on a single interrupt-request line to the RCPU.
Bus Monitor
internal to external accesses. It monitors the transfer acknowledge (TA) response time for internal
to external transfers. A transfer error acknowledge (TEA) is asserted if the TA response limit is
exceeded. This function can be disabled.
Decrementer
defined by the MPC500 architecture to provide a decrementer interrupt. This binary counter is
clocked by the same frequency as the time base (also defined by the MPC561/MPC563
architecture). The period for the DEC when driven by a 4-MHz oscillator can be up to 4295
seconds, which is approximately 71.6 minutes. Refer to
Time Base Counter
MPC500 architecture to provide a time base reference for the operating system or application
software. The TB has four independent reference registers that can generate a maskable interrupt
when the time-base counter reaches the value programmed in one of the four reference registers.
The associated bit in the TB status register will be set for the reference register which generated
the interrupt.
Real-Time Clock
time-of-day information to the operating system or application software. It is composed of a 45-bit
counter and an alarm register. A maskable interrupt is generated when the counter reaches the value
programmed in the alarm register. The RTC is clocked by the same clock as the PIT.
(Section 6.1.5, “Hardware Bus
(Section 6.1.6, “Decrementer
(Section 6.1.8, “Real-Time Clock
(Section 6.1.7, “Time Base
(Section 6.1.3, “USIU General-Purpose I/O
(Section 6.1.1, “System
MPC561/MPC563 Reference Manual, Rev. 1.2
(Section 6.1.4, “Enhanced Interrupt
(Section 6.1.2, “External Master
(DEC)”)—The DEC is a 32-bit decrementing counter
Monitor”)—The SIU provides a bus monitor to watch
Configuration”)—The USIU allows the
(TB)”)—The TB is a 64-bit counter defined by the
(RTC)”)—The RTC is used to provide
Table
6-6.
”)—The USIU provides 64 pins
Modes”)—External master
Controller”)—The interrupt
6-1