MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 391

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Figure
accessing internal space in the MPC561/MPC563.
Freescale Semiconductor
9-37,
1. Request Bus (BR)
2. Receives Bus Grant (BG) From Arbiter
3. Asserts Bus Busy (BB) if No Other Master is Driving
4. Assert Transfer Start (TS)
5. Drives Address and Attributes
Figure
The minimum number of wait states for such access is two clocks. The
accesses in these figures are valid for both peripheral mode and slave mode.
9-38, and
Figure 9-36. Basic Flow of an External Master Write Access
External Master
1. Drives Data
Figure 9-39
MPC561/MPC563 Reference Manual, Rev. 1.2
describe read and write cycles from an external master
NOTE
1. Asserts Transfer Acknowledge (TA)
1. Receives Data
Address in Internal
Memory Map
1. Receives Address
MPC500 Device
Yes
Asserts CSx
If In Range
Controller
Memory
No
External Bus Interface
9-51