MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 625

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Because the QSMCM contains a mix of supervisor and user registers, AACK is asserted for either
supervisor or user mode accesses, and the bus cycle remains internal. If a supervisor-only register is
accessed in user mode, the module responds as if an access had been made to an unauthorized register
location, and a bus error is generated.
15.4.4
The interrupt structure of the IMB3 supports a total of 32 interrupt levels that are time multiplexed on the
IRQB[0:7] lines as seen in
In this structure, all interrupt sources place their asserted level on a time multiplexed bus during four
different time slots, with eight levels communicated per slot. The ILBS[0:1] signals indicate which group
of eight are being driven on the interrupt request lines.
The QSMCM module is capable of generating one of the 32 possible interrupt levels on the IMB3. The
levels that the interrupt will drive can be programmed into the interrupt request level (ILDSCI and
ILQSPI) bits located in the interrupt configuration register (QDSCI_IL and QSPI_IL). This value
determines which interrupt signal (IRQB[0:7]) is driven onto the bus during the programmed time slot.
Figure 15-3
Freescale Semiconductor
IMB3 CLOCK
IMB3 IRQ[7:0]
QSMCM Interrupts
shows a block diagram of the interrupt hardware.
ILBS[0:1]
Figure
00
MPC561/MPC563 Reference Manual, Rev. 1.2
15-2.
Figure 15-2. QSMCM Interrupt Levels
01
IRQ
Table 15-3. Interrupt Levels
7:0
ILBS[0:1]
00
01
10
11
10
IRQ
15:8
23:16
11
IRQ
Levels
16:23
24:31
8:15
0:7
31:24
00
IRQ
01
IRQ
7:0
10
Queued Serial Multi-Channel Module
11
15-7