MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 922

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Development Support
software, by setting the corresponding software trap enable bit, or on the fly using the serial interface
implemented in the development port to set the corresponding development port trap enable bit.
External breakpoints can be generated by any of the peripherals of the system, including those found on
the MPC561/MPC563 or externally, and also by an external development system. Peripherals found on the
external bus use the serial interface of the development port to assert the external breakpoint.
In the RCPU, as in other RISC processors, saving/restoring machine state on the stack during exception
handling, is done mostly in software. When the software is in the middle of saving/restoring machine state,
MSR[RI] is cleared. Exceptions that occur and that are handled by the RCPU when MSR[RI] is clear result
in a non-restartable machine state. For more information refer to
Section 3.13.4,
“Exceptions.”
In general, breakpoints are recognized in the RCPU is only when MSR[RI] is set, which guarantees
machine restartability after a breakpoint. In this working mode breakpoints are said to be masked. There
are cases when it is desired to enable breakpoints even when MSR[RI] is clear, with the possible risk of
causing a non-restartable machine state. Therefore internal breakpoints have also a programmable
non-masked mode, and an external development system can also choose to assert a non-maskable external
breakpoint.
Watchpoints are not masked and therefore always reported on the external pins, regardless of the value of
MSR[RI]. The counters, although counting watchpoints, are part of the internal breakpoints logic and
therefore are not decremented when the RCPU is operating in the masked mode and MSR[RI] is clear.
Figure 23-1
shows the watchpoint and breakpoint support of the RCPU.
MPC561/MPC563 Reference Manual, Rev. 1.2
23-8
Freescale Semiconductor