MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 621

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Standard SCI features are listed below, followed by a list of additional features offered.
Standard SCI two-wire system features:
Standard SCI receiver features:
Standard SCI transmitter features:
QSMCM-additional SCI features:
QSMCM-enhanced SCI features:
15.2.1
The QSMCM module has an identical function to the MPC555. The MUXing of the pins is controlled by
the QPAPCS3 bit in the QSMCM pin assignment register (PQSPAR).
Freescale Semiconductor
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Programmable Transfer Delay — from 0.6 µs to 0.3 µs (at 28 MHz)
Programmable Queue Pointer
Continuous Transfer Mode — up to 256 bits
Optional on-chip expanded QSPI chip selects
Standard nonreturn-to-zero (NRZ) mark/space format
Advanced error detection mechanism (detects noise duration up to 1/16 of a bit-time)
Full-duplex operation
Software selectable word length (8- or 9-bit words)
Separate transmitter and receiver enable bits
May be interrupt driven
Four separate interrupt enable bits
Two independent operating SCI modules
Receiver wakeup function (idle or address mark bit)
Idle-line detect
Framing, noise, and overrun error detect
Receive data register full flag
Transmit data register empty flag
Transmit complete flag
Send break
13-bit programmable baud-rate modulus counter
Even/odd parity generation and detection
Two idle-line detect modes
Receiver active flag
16 register receive buffer on one SCI
16 register transmit buffer on one SCI
MPC561/MPC563 QSMCM Details
MPC561/MPC563 Reference Manual, Rev. 1.2
Queued Serial Multi-Channel Module
15-3